Product line 04
India is in the middle of the largest fibre-to-the-home build-out in its history, and it is being executed on entirely imported access silicon — from a supply base that is consolidating rather than expanding. We are designing an indigenous passive optical network access SoC family to close that gap, with the security assurance the regulatory framework already demands built into the die rather than bolted around it.
The case
01
National rural broadband and private fibre roll-outs are adding subscribers at pace, making India one of the fastest-growing optical terminal markets in the world. Every connection terminates in an optical network terminal, and every terminal contains a PON access SoC.
02
Product lines in this segment have been discontinued or transferred following industry consolidation, and equipment makers are converging on a small number of foreign suppliers for the one component without which none of the equipment functions.
03
Telecom equipment sold in India must be certified for testing and conformance, must satisfy the national telecom security assurance requirements, and must come from designated trusted sources. Indian manufacturers are bound by all three with no indigenous access silicon to build on.
A national broadband programme resting on one foreign vendor for its most critical component is a concentration risk, not a procurement detail.
Product family
The IP cores are deliverable to equipment and SoC houses ahead of any silicon existing. The terminal SoCs follow on the same platform, so the second part reuses the first part’s proven flow rather than restarting it.
Media access control for both GPON and XGS-PON: downstream framing and descrambling, upstream burst assembly, ranging and activation, dynamic bandwidth allocation reporting, PON-layer encryption and forward error correction — with a terminal management and control interface engine and a standards-based remote management agent. Architected so one datapath serves both line rates.
The compliance block, specified against the security assurance requirements as they apply to customer premises equipment: a verified secure boot chain from an immutable root, signed firmware update with anti-rollback enforcement, protected storage for operator credentials and configuration, hardened management interfaces, secure logging and factory-reset integrity. Delivered as a licensable core and integrated into both SoCs.
A digital and mixed-signal system-on-chip on a 40 nm CMOS process, sitting at the subscriber end of the network: PON MAC, an indigenous RISC-V applications processor subsystem, a hardware packet engine and integrated Ethernet switch with gigabit MACs, DDR3/DDR4 controller and PHY, flash, USB, voice support, and the trust subsystem. Delivered as clean GDSII, fabricated silicon, and packaged and tested parts.
A symmetric 10 Gbit/s variant reusing the proven platform and physical-design flow, adding a 10G-class SerDes and burst-mode optical interface control. Addresses the upgrade cycle that follows as operators move subscribers to 10 Gbit/s services.
Inside the terminal SoC
A terminal SoC terminates the fibre, converts between the access network and the home network, and presents a managed, secure device to the operator. That is three quite different engineering problems sharing one power and area budget.
Fig. 07 — terminal SoC block diagram
Programme
The design and sign-off flow established in the first year is reused for the 10G variant in the second. That is where both the schedule risk and the tool cost concentrate — and it is why the family is sequenced this way rather than run in parallel.
| Phase | Work | Exit criterion |
|---|---|---|
| Architecture & MAC RTL | Specification freeze against the optical access and management standards and against the applicable conformance and assurance requirements. RTL of the downstream and upstream datapath, framing, ranging and activation. Lint and clock-domain-crossing closure. FPGA prototype. | Framing, ranging and activation verified against the conformance suite in simulation; prototype achieves link-up and sustained transfer against a commercial line terminal. |
| Trust block & SoC integration | Bandwidth allocation, PON-layer encryption, error correction and the management engine completed. Trust subsystem RTL — boot chain, signed update, credential storage, hardened interfaces. Full SoC integration, synthesis and power-intent verification. | Management interoperability against multiple line terminal implementations; boot and signed-update chain verified end to end; netlist meets timing, area and power targets. |
| Physical implementation | Floorplan, place-and-route, clock tree synthesis, multi-corner multi-mode timing analysis, power grid, IR-drop and electromigration analysis, parasitic extraction, and hard-macro integration. | Placed-and-routed database with timing closed across all corners and modes; IR-drop and electromigration within limits; power targets met with extracted parasitics. |
| Tape-out | Test structure insertion with compressed scan and built-in self-test, pattern generation closure, full-chip design-rule, layout-versus-schematic and electrical rule checking, GDSII release, and test program and load board development. | Fault coverage target met at the required compression ratio; clean full-chip physical verification; tape-out confirmed; test program correlated against simulation. |
| Bring-up & characterisation | Silicon bring-up, functional verification and characterisation across voltage and temperature. Optical link testing and interoperability against multiple line terminal vendors. 10G architecture and SerDes design starts in parallel. | Silicon achieves link-up, ranging and sustained line-rate throughput; interoperability demonstrated across several line terminal platforms; characterisation complete over the commercial range. |
| Certification & field trial | Conformance certification submission and security assurance evidence package. Reliability sign-off, yield and failure diagnosis on returned silicon. Field trial in a live operator deployment with an equipment manufacturer. | Certification obtained or submission accepted; assurance evidence accepted; field trial report covering a defined subscriber count over a defined period. |
| 10G implementation | Full-chip integration, synthesis, place-and-route, timing and power sign-off and physical verification for the XGS-PON variant, reusing the established platform and flow. | Timing closed across corners; SerDes meets jitter and eye-mask specification in simulation and on test structures; clean physical verification. |
| Release & transfer | 10G tape-out. Reference board designs, Linux board support package, management stacks and integration guides released. Technology transfer package delivered; networking IP contributed back to the national IP repository. | Reference designs and software development kit adopted by an equipment manufacturer; the GPON part released for volume production. |
Design position
Rather than importing a generic secure element intended for another market, the trust subsystem is specified against the assurance requirements as they apply to customer premises equipment — so the compliance evidence a manufacturer needs is produced by the silicon, not assembled around it afterwards.
Terminals here fail for reasons that have little to do with protocol conformance: ambient temperature, unreliable mains and surge events, dust ingress, long unattended operation. Wide-temperature operation, brown-out tolerance, in-field self-test and remote diagnostics are product requirements from the start rather than retrofits.
The MAC and trust cores are licensable to equipment and SoC houses before any silicon exists; packaged parts follow. A manufacturer can adopt the IP into their own design or take the SoC, without waiting on the other track.
Reference board designs, a Linux board support package, the management stacks and integration guides ship with the part. The intent is that an existing terminal design can move to this silicon as an engineering change, not a new programme.
We are interested in early conversations with equipment manufacturers, operators and SoC houses — on IP licensing, design-in, interoperability testing, or field trial participation.